The present invention relates to methods and apparatus for screening a static random access memory (SPAM) and, in particular, for improving the quality of the screening process so as to better detect leakage paths from the bit line of the SRAM to ground.
With reference to FIGS. 1A-1B, SRAM memory cells store data in the form of complementary low voltage and high voltage at opposite sides of the cell. An SRAM, unlike dynamic random access memory (DRAM), maintains the data content of the memory calls as long as power is applied to the cell. DRAM memory cells, on the other hand, are periodically refreshed with the stored data content.
An SRAM cell includes a “true” node associated with a bit line (BLT) of the SRAM memory and a complementary node associated with a complementary bit line (BLC) of the SRAM memory. When the true node is read as a high voltage, the value of the SRAM memory cell is digital one. If the true node is read as a low voltage, the value of the SRAM memory cell is a digital zero. Each memory cell of a conventional SRAM memory employs an anti-parallel inverter transistor latch circuit coupled across the BLT bus and the BLC bus. A pair of series-coupled transistors connect/disconnect the cell to the BLT and BLC bus. The series transistors are gated via the word line (WL). During write and read cycles, a conventional SRAM memory system will employ a pre-charge circuit to drive the bit line BLT and the complementary bit line BLC to a power supply voltage of the SRAM memory, Vdd, before data is written to the memory cell. During the time that the data is actually written to the SRAM memory cell, the word line WL is true and a write buffer drives the bit line BLT and the complementary bit line BLC. During the read operation, the word line WL is again true and the active components of the SRAM memory cell itself will drive the bit line BLT, which is sensed to determine the value of the stored data bit in the cell.
A sense amplifier detects the level of the local BLT to determine the stored data in a given cell. The conventional circuitry for sensing the contents of each memory cell via the bit line BLT includes a basic sensing circuit, which compares a predetermined voltage (V threshold) to the voltage on BLT.
As illustrated in FIG. 1B, without leakage, a stored logic level H is sensed above the threshold and is correctly detected as passing the test. With leakage, however, the pull-up circuitry (e.g., the word line WL, write driver, etc.) tends to counteract the leakage draw and the stored logic level H may still be sensed above the threshold—which is not a desirable condition because it would be better to sense this situation as a failure. Unfortunately, conventional sensing circuitry and protocols do not take into consideration whether there is excessive leakage from the BLT to ground during testing of the SRAM.
The problem of incorrectly determining that a cell is operating properly (i.e., a false positive or pass) becomes significantly worse as the frequency of the clock increases and the size of the SRAM increases, which is an ongoing circumstance as higher and higher memory performance remains a design goal. Accordingly, there is a need in the art for a new approach to screening SRAM memory cells in order to detect memory cells in which the leakage characteristics of the cell are unacceptably high.